1. Field of the Invention
The present invention relates to a control method for a memory system, in particular, the present invention relates to a control method for the wear-leveling of a memory.
2. Description of the Related Art
Non-volatile memory is used for storing data, such as flash memory. The flash memory is usually used as a storage device, such as memory card, USB interface portable disk, and solid state disk, etc.
Reference is made to FIG. 1, which shows a schematic diagram of the system structure of the memory system of the prior art. As shown in FIG. 1, the memory system 13 is coupled with a host 11 so that the data can be accessed between the memory system 13 and the host 11. The host 11 uses the logical address to represent the storage location of the data, and the memory system 11 uses the physical address to represent the storage location of the data. The memory system 13 includes a storage module 131 and a control module 133. The storage module 131 is used for storing data. When the host 11 wants to access data in the storage module 131, the control module 133 converts the logical address from the host 11 into the physical address for the storage module 131 to access data.
Because the ranges of the logical address and the physical address are very large, it is time-consuming to convert the logical address into the corresponding physical address. Therefore, the storage module 131 is divided into a plurality of physical blocks, and the storage space of the host 11 is also divided into a plurality of logical blocks. Each block includes a plurality of addresses. The block is used as a unit to convert the logical address into the physical address to improve the memory management. However, it is still time-consuming to convert the logical address into the corresponding physical address within a large memory space so that segment is developed to overcome the above problem.
In the memory system 13 used the segment as a unit, the storage module 131 is divided into a plurality of physical segments, and the storage space in the host 11 also is divided into a plurality of logical segments. Each of the logical segments respectively corresponds to one physical segment, and each segment includes a plurality of blocks. Reference is made to FIG. 2, which is a schematic diagram of the segment logical to physical address conversion. As shown in FIG. 2, after the logical addresses of the storage space in the host 11 is calculated, the addresses is divided into 8000 logical block addresses (LBA). 250 logical block addresses is used as a unit and is defined as a logical segment. Therefore, 32 logical segments LS0, LS1, . . . , LS31 are obtained. The storage module 131 in the memory system 13 also is divided into 32 physical segments PS0, PS1, . . . , PS31 by the same concept. Each physical segment has 256 continuous physical block addresses (PBA). Wherein, 250 physical blocks correspond to the logical blocks, and 6 physical blocks are used as free blocks for recording control data or replacing the damaged physical blocks.
In the memory system 13, the free block stores the L2P mapping table that records the mapping relation between the physical blocks in each physical segment and the logical blocks. The logical segment LS0 records the logical addresses 0˜63999 that are divided into 250 logical block (LBA 0˜249). The L2P mapping table records the mapping relation between the 250 logical blocks and the 256 physical blocks (PBA=0˜255). By referring to the L2P mapping table, the logical address can be rapidly and exactly mapped to the physical address.
By using the segment concept, the quantity of the memory conversion units is reduced and it does not need to provide a lot of storage space to store the L2P mapping table. However, the erase cycles of the flash memory is limited. The method for using the storage space and the different updating frequency for recording data in the host 11 both will affect the storage space location in the storage module 131 so that the erase cycles for each physical block are different. Moreover, each physical segment includes a fixed range physical blocks and a fixed mapping way. For example, logical blocks LBA=0˜249 in logical segment LS0 is mapped to the physical blocks PBA=0˜255 in the physical segments PS0. Thereby, even through the erase cycles of the physical blocks in a single physical segment can be uniform, a specific physical segment still will be erased too much times and worn due to the fixed range physical segment structure. The usage life of the memory system 13 is shortened.